24LC128-ISLASHCS15K datasheet(9/38 Pages) MICROCHIP

9 / 38 page

 2010 Microchip Technology Inc.

DS21191S-page 9

24AA128/24LC128/24FC128

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (This feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the Start bit and control byte must

be resent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 7-1 for

flow diagram.

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

High Byte

Address

Low Byte

Data

x = “don’t care” bit

S 1010

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

High Byte

Address

Low Byte

Data Byte 0

Data Byte 63

x = “don’t care” bit

S 1 010

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24LC128-I/CS15K 데이터시트(PDF) 9 Page - Microchip Technology

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