Block Guide — S12BDM V4

9

Section 2 External Signal Description

2.1 Overview

A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used

for instruction tagging. These pins are part of the Multiplexed External Bus Interface (MEBI) sub-block

and all interfacing between the MEBI and BDM is done within the Core interface boundary. Functional

descriptions of the pins are provided below for completeness.

•

BKGD — Background interface pin

•

TAGHI — High byte instruction tagging pin

•

TAGLO — Low byte instruction tagging pin

•

BKGD and TAGHI share the same pin.

•

TAGLO and LSTRB share the same pin.

NOTE:

Generally these pins are shared as described, but it is best to check the chip

description to make certain. All chips at the time of this writing have followed this

pin sharing scheme.

2.2 Detailed Signal Descriptions

2.2.1 Background Interface Pin (BKGD)

Debugging control logic communicates with external devices serially via the single-wire background

interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and

special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the

background debug mode.

2.2.2 High Byte Instruction Tagging Pin (TAGHI)

This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling

edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction

queue.

2.2.3 Low Byte Instruction Tagging Pin (TAGLO)

This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is

enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word

being read into the instruction queue.