PIC16F685-ESLASHP datasheet(28/306 Pages) MICROCHIP

28 / 306 page

PIC16F631/677/685/687/689/690

DS41262E-page 26

2.2

Data Memory Organization

The data memory (see Figures 2-6 through 2-8) is

partitioned into four banks which contain the General

Purpose Registers (GPR) and the Special Function

Registers (SFR). The Special Function Registers are

located in the first 32 locations of each bank. The

General Purpose Registers, implemented as static

RAM, are located in the last 96 locations of each Bank.

Bank 2 and 1F0h-1FFh in Bank 3 point to addresses

70h-7Fh in Bank 0. The actual number of General

Purpose Resisters (GPR) in each Bank depends on the

device. Details are shown in Figures 2-4 through 2-8.

All other RAM is unimplemented and returns ‘0’ when

read. RP<1:0> of the STATUS register are the bank

select bits:

RP1

RP0

→ Bank 0 is selected

→ Bank 1 is selected

→ Bank 2 is selected

→ Bank 3 is selected

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 128 x 8 in the

PIC16F687

and

256

the

PIC16F685/PIC16F689/PIC16F690. Each register is

accessed, either directly or indirectly, through the File

Select Register (FSR) (see Section 2.4 “Indirect

Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Tables 2-1

through 2-4). These registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Registers related to the operation of peripheral features

are described in the section of that peripheral feature.

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