LTC6992-2 datasheet(21/32 Pages) LINER

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LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

69921234p

APPLICATIONS INFORMATION

At the other extreme, it is not recommended to operate

the master oscillator beyond 2MHz because the accuracy

of the DIV pin ADC will suffer.

Pulse Width Modulation Bandwidth and Settling Time

The LTC6992 will respond to changes in VMOD up to a –3dB

bandwidth of TBD (see Figure 10). This makes it easy to

stabilize a feedback loop around the LTC6992, since it

does not introduce a low frequency pole.

Duty cycle settling time depends on the master oscillator

frequency. Following a ±100mV step change in VMOD, the

duty cycle takes approximately TBD master clock cycles

(TBD • tMASTER) to settle to within 1% of the final value.

An example is shown in Figure 11.

Frequency Modulation and Settling Time

In addition to pulse-width modulation, the LTC6992 can

be frequency modulated by varying ISET. The LTC6992

will respond to changes in ISET up to a –3dB bandwidth

of TBD • fOUT (see Figure 12).

Following a 2x or 0.5x step change in ISET, the output

frequency takes approximately TBD master clock cycles

(TBD • tMASTER) to settle to within 1% of the final value.

An example is shown in Figure 13.

Figure 13. Frequency Change Settling Time

PLACEHOLDER

Figure 10. PWM Frequency Response

Figure 11. PWM Settling Time

Figure 12. Frequency Modulation Bandwidth

PLACEHOLDER

LTC6992-2 데이터시트(PDF) 21 Page - Linear Technology