ADT7467ARQZ-R7 datasheet(70/77 Pages) ONSEMI

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ADT7467

Rev. 3 | Page 70 of 77 | www.onsemi.com

Table 38. Register 0x63—Enhanced Acoustics Register 2 (Power-On Default = 0x00)

Bit

Name

R/W1

Description

<2:0>

ACOU3

Read/write

These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to

its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect

enhances the acoustics of the fan being driven by the PWM3 output.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

<3>

EN3

Read/write

When this bit is 1, acoustic enhancement is enabled on PWM3 output.

<6:4>

ACOU2

Read/write

These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to

its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect

enhances the acoustics of the fans being driven by the PWM2 output.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

<7>

EN2

Read/write

When this bit is 1, acoustic enhancement is enabled on PWM2 output.

1 This register becomes a read-only register when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 39. PWM Minimum Duty Cycle Registers

R/W1

Description

Power-On Default

0x64

Read/write

PWM1 minimum duty cycle.

0x80 (50% duty cycle)

0x65

Read/write

PWM2 minimum duty cycle.

0x80 (50% duty cycle)

0x66

Read/write

PWM3 minimum duty cycle.

0x80 (50% duty cycle)

1 These registers become read-only registers when the ADT7467 is in automatic fan control mode.

Table 40. Register 0x64, Register 0x65, and Register 0x66—PWM1, PWM2, and PWM3 Minimum Duty Cycle Registers

Bit

R/W1

Description

<7:0>

Read/write

These bits define the PWMMIN duty cycle for PWMx.

0x00 = 0% duty cycle (fan off ).

0x40 = 25% duty cycle.

0x80 = 50% duty cycle.

0xFF = 100% duty cycle (fan full speed).

1 These registers becomes a read-only register when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

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