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ADT7484AARMZ-R7 데이터시트(PDF) 3 Page - ON Semiconductor |
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ADT7484AARMZ-R7 데이터시트(HTML) 3 Page - ON Semiconductor |
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3 / 14 page ![]() ADT7484A/ADT7486A http://onsemi.com 3 ADT7484A PIN ASSIGNMENT Pin No. Mnemonic Type Description 1 VCC Power supply 3.3 V ± 10%. 2 GND Ground Ground Pin. 3 D1+ Analog input Positive Connection to Remote Temperature Sensor. 4 D1− Analog input Negative Connection to Remote Temperature Sensor. 5 ADD1 Digital input SST Address Select. 6 RESERVED Reserved Connect to Ground. 7 ADD0 Digital input SST Address Select. 8 SST Digital input/output SST Bidirectional Data Line. ADT7486A PIN ASSIGNMENT Pin No. Mnemonic Type Description 1 VCC Power supply 3.3 V ± 10%. 2 GND Ground Ground Pin. 3 D1+ Analog input Positive Connection to Remote 1 Temperature Sensor. 4 D1− Analog input Negative Connection to Remote 1 Temperature Sensor. 5 D2+ Analog input Positive Connection to Remote 2 Temperature Sensor. 6 D2− Analog input Negative Connection to Remote 2 Temperature Sensor. 7 ADD1 Analog input SST Address Select. 8 RESERVED Analog input Connect to Ground. 9 ADD0 Digital input SST Address Select. 10 SST Digital input/output SST Bidirectional Data Line. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, = VCC = VMIN to VMAX, unless otherwise noted) Parameter Conditions Min Typ Max Unit Power Supply Supply Voltage, VCC 3.0 3.3 3.6 V Undervoltage Lockout Threshold 2.8 V Average Operating Supply Current, IDD Continuous conversions 3.8 5.0 mA Temperature-to-Digital Converter Local Sensor Accuracy 40°C ≤ TA ≤ 70°C, VCC = 3.3 V ±5% +1.0 ±1.75 °C −40°C ≤ TA ≤ +100°C ±4.0 °C Remote Sensor Accuracy −40°C ≤ TD ≤ +125°C; TA = 25°C; VCC = 3.3 V ±1.0 °C −40°C ≤ TD ≤ +125°C; −40 ≤ TA ≤ 70°C, VCC = 3.3 V ±5% +1.0 ±1.75 °C −40°C ≤ TD ≤ +125°C; −40 ≤ TA ≤ +100°C ±4.0 °C Remote Sensor Source Current Low level Mid level High level 12 80 204 mA Resolution 0.016 °C Series Resistance Cancellation The ADT7484A and ADT7486A cancel 1.5 kW in series with the remote thermal diode 1.5 kW 1. Guaranteed by design, not production tested. 2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse. 3. Devices compatible with hold time specification as driven by SST originator. |
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