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ADT7485AARMZ-R7 데이터시트(PDF) 3 Page - ON Semiconductor |
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ADT7485AARMZ-R7 데이터시트(HTML) 3 Page - ON Semiconductor |
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3 / 12 page ![]() ADT7485A http://onsemi.com 3 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Parameter Test Conditions/Comments Min Typ Max Unit Power Supply Supply Voltage, VCC 3.0 3.3 3.6 V Undervoltage Lockout Threshold 2.8 V Average Operating Supply Current, IDD Continuous conversions 3.8 5.0 mA Temperature−to−Digital Converter Local Sensor Accuracy 40°C ≤ TA ≤ 70°C; VCC = 3.3 V ±5% −40°C ≤ TA ≤ +100°C +1.0 ±1.75 ±4.0 °C Remote Sensor Accuracy −40°C ≤ TD ≤ +125°C; TA = 25°C; VCC = 3.3 V −40°C ≤ TD ≤ +125°C; −40 ≤ TA ≤ 70°C; VCC = 3.3 V ±5% −40°C ≤ TD ≤ +125°C; −40 ≤ TA ≤ +100°C +1.0 ±1.0 ±1.75 ±4.0 °C Remote Sensor Source Current Low level Mid level High level 12 80 204 mA Resolution 0.016 °C Series Resistance Cancellation The ADT7485A cancels 1.5 kW in series with the remote thermal diode 1.5 kW Digital Input (ADD) Input High Voltage, VIH 2.3 V Input Low Voltage, VIL 0.8 V Input High Current, IIH VIN = VCC −1.0 mA Input Low Current, IIL VIN = 0 1.0 mA Pin Capacitance 5.0 pF Analog−to−Digital Converter (Including Multiplexer and Attenuators) Total Unadjusted Error (TUE) 12 V and 5.0 V channels For all other channels ±2.0 ±1.5 % Differential Non−linearity (DNL) 10 bits ±1.0 LSB Power Supply Sensitivity ±0.1 %/V Conversion Time (Voltage Input) (Note 1) Averaging enabled 11 ms Conversion Time (Local Temperature) (Note 1) Averaging enabled 12 ms Conversion Time (Remote Temperature) (Note 1) Averaging enabled 38 ms Total Monitoring Cycle Time (Note 1) Averaging enabled 145 ms Input Resistances VCCP and 2.5V Channels 5.0 V Channel 12 V Channel 80 95 180 110 120 230 140 150 280 kW Digital I/O (SST Pin) Input High Voltage , VIH 1.1 V Input Low Voltage, VIL 0.4 V Hysteresis (Note 1) Between input switching levels 150 mV Output High Voltage, VOH ISOURCE = 6 mA (maximum) 1.1 1.9 V 1. Guaranteed by design, not production tested. 2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse. 3. Device is compatible with hold time specification as driven by SST originator. |
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