ADT7490ARQZ-R7 datasheet(60/75 Pages) ONSEMI

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ADT7490

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Table 51. Register 0x63 — Enhanced Acoustics Register 2 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[2:0]

ACOU2

R/W

Assuming that PWMx is associated with the local temperature channel, these bits define the

maximum rate of change of the PWMx output for local temperature−related changes. Instead of

the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the

rate determined by these bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0

Bit Code

Time for 0% to 100%

000 = 1

001 = 2

010 = 3

011 = 4

100 = 8

101 = 12

110 = 24

111 = 48

37.5 sec

18.8 sec

12.5 sec

7.5 sec

4.7 sec

3.1 sec

1.6 sec

0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1

Bit Code

Time for 0% to 100%

000 = 1

001 = 2

010 = 3

011 = 4

100 = 8

101 = 12

110 = 24

111 = 48

52.2 sec

26.1 sec

17.4 sec

10.4 sec

6.5 sec

4.4 sec

2.2 sec

1.1 sec

[3]

EN2

R/W

When this bit is 1, smoothing is enabled on the local temperature channel.

[6:4]

ACOU3

R/W

Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define

the maximum rate of change of the PWMx output for Remote 2 Temperature related

changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it

ramps gracefully at the rate determined by these bits. This feature ultimately enhances the

acoustics of the fan.

[7]

EN3

R/W

When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 52. PWM Minimum Duty Cycle Registers

R/W (Note 1)

Description

Power−On Default

0x64

R/W

PWM1 minimum duty cycle.

0x80 (50% duty cycle)

0x65

R/W

PWM2 minimum duty cycle.

0x80 (50% duty cycle)

0x66

R/W

PWM3 minimum duty cycle.

0x80 (50% duty cycle)

1. These registers become read-only when the ADT7490 is in automatic fan control mode.

Table 53. Register 0x64, Register 0x65, and Register 0x66 — PWM1, PWM2, and PWM3 Min Duty Cycles

(Power−On Default = 0x80)

R/W (Note 1)

Description

[7:0]

R/W

These bits define the PWMMIN duty cycle for PWMx.

0x00 = 0% duty cycle (fan off).

0x40 = 25% duty cycle.

0x80 = 50% duty cycle.

0xFF = 100% duty cycle (fan full speed).

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

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