UJA1076 datasheet(5/47 Pages) NXP

5 / 47 page

UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

5 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

Pinning information

5.1 Pinning

5.2 Pin description

Fig 2.

Pin configuration

UJA1076

i.c.

BAT

i.c.

VEXCTRL

i.c.

TEST2

VEXCC

i.c.

WBIAS

RSTN

i.c.

INTN

i.c.

SDI

SPLIT

SDO

GND

SCK

CANL

SCSN

CANH

TXDC

RXDC

WAKE2

TEST1

WAKE1

WDOFF

LIMP

015aaa109

Table 2.

Pin description

Symbol

Description

i.c.

internally connected; should be left floating

i.c.

internally connected; should be left floating

i.c.

internally connected; should be left floating

voltage regulator output for the microcontroller (5 V or 3.3 V depending on

SBC version)

i.c.

internally connected; should be left floating

RSTN

reset input/output to and from the microcontroller

INTN

interrupt output to the microcontroller

enable output

SDI

SPI data input

SDO

SPI data output

SCK

SPI clock input

SCSN

SPI chip select input

TXDC

CAN transmit data input

RXDC

CAN receive data output

TEST1

test pin; pin should be connected to ground

WDOFF

WDOFF pin for deactivating the watchdog

LIMP

limp home output

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