DSP56303 datasheet(49/108 Pages) FREESCALE

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AC Electrical Characteristics

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-29

2.5.5.5 Asynchronous Bus Arbitration Timings

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG

is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.

Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251

ensures that overlaps are avoided.

Table 2-15.

Asynchronous Bus Timings1, 2

No.

Characteristics

Expression3

100 MHz4

Unit

Min

Max

250

BB assertion window from BG input deassertion5

2.5

× Tc + 5

—

251

Delay from BB assertion to BG assertion

× Tc + 5

—

Notes:

Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.

If Asynchronous Arbitration mode is active, none of the timings in Table 2-14 is required.

An expression is used to compute the maximum or minimum value listed, as appropriate.

Asynchronous Arbitration mode is recommended for operation at 100 MHz.

In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the

non-overlap manner shown in Figure 2-26.

Figure 2-26.

Asynchronous Bus Arbitration Timing

BG1

251

BG2

250

250+251

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