68HC05P4A datasheet(39/83 Pages) FREESCALE

39 / 83 page

GENERAL RELEASE SPECIFICATION

7-2

Rev. 2.0

In master mode, the format is identical except that the SCK pin is an output and

the shift clock now originates internally. The master mode transmission frequency

is ﬁxed at E/4.

7.1.2 Serial Data Out (SDO)

A mask programmable option will be included to allow data to be transmitted in

either MSB ﬁrst format or LSB ﬁrst format. In either case, the state of the SDO pin

always will reﬂect the value of the ﬁrst bit received on the previous transmission if

there was one. Prior to enabling the SIOP, PB5 can be initialized to determine the

beginning state if necessary. While the SIOP is enabled, PB5 can not be used as

a standard output since that pin is coupled to the last stage of the serial shift

presented to the output pin.

7.1.3 Serial Data In (SDI)

The SDI pin becomes an input as soon as the SIOP is enabled. New data may be

presented to the SDI pin on the falling edge of SCK. Valid data must be present at

least 100 ns before the rising edge of the clock and remain valid for 100 ns after

the edge.

SDO

BIT 1

BIT 2

BIT 3

BIT 7

SCK

BIT 8

SDI

BIT 1

BIT 2

BIT 3

BIT 7

BIT 8

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68HC05P4A 데이터시트(PDF) 39 Page - Freescale Semiconductor, Inc