56F8013 datasheet(21/126 Pages) FREESCALE

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56F8013/56F8011 Signal Pins

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

TDO

(GPIOD1)

Output

Input/

Output

Test Data Output — This tri-stateable output pin provides a serial

output data stream from the JTAG/EOnCE port. It is driven in the

shift-IR and shift-DR controller states, and changes on the falling

edge of TCK.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TDO.

GPIOB0

(SCLK)

(SCL3)

Input/

Output

Input/

Output

Input/

Output

Input with

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

SPI Serial Clock — In the master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin serves as

the data clock input. A Schmitt trigger input is used for noise

immunity.

Serial Data — This pin serves as the I2C serial clock.

After reset, the default state is GPIOB0. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

3. This signal is also brought out on the GPIOB7 pin.

GPIOB1

(SS)

(SDA4)

Input/

Output

Input

Input/

Output

Input with

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

SPI Slave Select — SS is used in slave mode to indicate to the SPI

module that the current transfer is to be received.

Serial Clock — This pin serves as the I2C serial data line.

After reset, the default state is GPIOB1. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

4. This signal is also brought out on the GPIOB6 pin.

Return to Table 2-2

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

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