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56F8036 데이터시트(PDF) 21 Page - Freescale Semiconductor, Inc |
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56F8036 데이터시트(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 164 page ![]() 56F8036 Signal Pins 56F8036 Data Sheet, Rev. 6 Freescale Semiconductor 21 2.2 56F8036 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 31 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 38 VSS 19 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers. VSS 30 VSS 39 VDDA 12 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. VSSA 13 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules. VCAP 20 Supply Supply VCAP — Connect this pin to a 2.2μF or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. See Section 10.2.1. VCAP 37 RESET (GPIOA7) 23 Input Input/Open Drain Output Input, internal pull-up enabled Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the chip is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. Return to Table 2-2 |
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