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PC912XDP512F0MPVR 데이터시트(PDF) 206 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 206 Page - Freescale Semiconductor, Inc |
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206 / 1348 page ![]() Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 206 Freescale Semiconductor 6.5 Interrupts 6.5.1 Incoming Interrupt Requests XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide. 6.5.2 Outgoing Interrupt Requests There are three types of interrupt requests which can be triggered by the XGATE module: 4. Channel interrupts For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector (XGIF, see Section 6.3.1.4, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to the S12X_CPU when the XGATE has completed one of its tasks. 5. Software triggers Software triggers are interrupt flags, which can be set and cleared by software (see Section 6.3.1.5, “XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software. 6. Software error interrupt The software error interrupt signals to the S12X_CPU the detection of an error condition in the XGATE application code (see Section 6.4.5, “Software Error Detection”). All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL, see Section 6.3.1.1, “XGATE Control Register (XGMCTL)”). 6.6 Debug Mode The XGATE debug mode is a feature to allow debugging of application code. 6.6.1 Debug Features In debug mode the RISC core will be halted and the following debug features will be enabled: • Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)1 All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values. 1. Only possible if MCU is unsecured |
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