PC912XDP512F0MPVR datasheet(55/1348 Pages) FREESCALE

55 / 1348 page

Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

NOTE

For devices assembled in 80-pin and 112-pin packages all non-bonded out

pins should be conﬁgured as outputs after reset in order to avoid current

drawn from ﬂoating inputs. Refer to Table 1-7 for affected pins.

1.2.3

Detailed Signal Descriptions

NOTE

This section describes all pins which are availabe on the cover part

MC9S12XDP512 in 144-pin LQFP package. For modules and pinout

explanations of the different family members refer to E.7 Pinout

explanations: and E.5 Peripheral Sets S12XD - Family and E.6 Peripheral

Sets S12XA & S12XB - Family

1.2.3.1

EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the crystal output.

1.2.3.2

RESET — External Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a

known start-up state. As an output it is driven ;ow to indicate when any internal MCU reset source triggers.

The RESET pin has an internal pullup device.

PS5

MOSI0

—

VDDX

PERS/

PPSS

Port S I/O, MOSI of SPI0

PS4

MISO0

—

VDDX

PERS/

PPSS

Port S I/O, MISO of SPI0

PS3

TXD1

—

VDDX

PERS/

PPSS

Port S I/O, TXD of SCI1

PS2

RXD1

—

VDDX

PERS/

PPSS

Port S I/O, RXD of SCI1

PS1

TXD0

—

VDDX

PERS/

PPSS

Port S I/O, TXD of SCI0

PS0

RXD0

—

VDDX

PERS/

PPSS

Port S I/O, RXD of SCI0

PT[7:0]

IOC[7:0]

—

VDDX

PERT/

PPST

Disabled Port T I/O, timer channels

Table 1-7. Signal Properties Summary (Sheet 4 of 4)

Name

Function 1

Name

Function 2

Name

Function 3

Name

Function 4

Name

Function 5

Power

Supply

Internal Pull

Resistor

Description

CTRL

Reset

State

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