| 전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 265 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 265 Page - Freescale Semiconductor, Inc |
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265 / 1348 page ![]() Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 265 Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’s complement on a general purpose register. CCR Effects Code and CPU Cycles NEG Two’s Complement NEG NZ V C ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS[15] & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise RS[15] | RD[15]new Source Form Address Mode Machine Code Cycles NEG RD, RS TRI 0 0 0 1 1 RD 0 0 0 RS 0 0 P NEG RD TRI 0 0 0 1 1 RD 0 0 0 RD 0 0 P |
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