PC912XDP512F0MPVR datasheet(373/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

373

Read: Anytime

Write: Anytime

NOTE

Write these bits only when the corresponding channel is disabled.

8.3.2.6

PWM Control Register (PWMCTL)

The PWMCTL register provides for various control of the PWM module.

Read: Anytime

Write: Anytime

There are three control bits for concatenation, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the

high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers

become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel

2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are

concatenated, channel 0 registers become the high order bytes of the double byte channel.

See Section 8.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM

Function.

NOTE

Change these bits only when both corresponding channels are disabled.

Table 8-7. PWMCAE Field Descriptions

Field

Description

7–0

CAE[7:0]

Center Aligned Output Modes on Channels 7–0

0 Channels 7–0 operate in left aligned output mode.

1 Channels 7–0 operate in center aligned output mode.

76543210

CON67

CON45

CON23

CON01

PSWAI

PFRZ

Reset

00000000

= Unimplemented or Reserved

Figure 8-8. PWM Control Register (PWMCTL)

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