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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 397 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 397 Page - Freescale Semiconductor, Inc |
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397 / 1348 page  Chapter 9 Inter-Integrated Circuit (IICV2) Block Description MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 397 9.2 External Signal Description The IICV2 module has two external pins. 9.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 9.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 9.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers for the IIC module. 9.3.1 Module Memory Map The memory map for the IIC module is given below in Table 1-1. The address listed for each register is the address offset.The total address for each register is the sum of the base address for the IIC module and the address offset for each register. |
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