PC912XDP512F0MPVR datasheet(428/1348 Pages) FREESCALE

428 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

428

Freescale Semiconductor

10.3.2.3

MSCAN Bus Timing Register 0 (CANBTR0)

The CANBTR0 register conﬁgures various CAN bus timing parameters of the MSCAN module.

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

SLPAK

Sleep Mode Acknowledge — This ﬂag indicates whether the MSCAN module has entered sleep mode (see

Section 10.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake ﬂag for the SLPRQ sleep mode request.

Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will

clear the ﬂag if it detects activity on the CAN bus while in sleep mode.

0 Running — The MSCAN operates normally

1 Sleep mode active — The MSCAN has entered sleep mode

INITAK

Initialization Mode Acknowledge — This ﬂag indicates whether the MSCAN module is in initialization mode

(see Section 10.4.5.5, “MSCAN Initialization Mode”). It is used as a handshake ﬂag for the INITRQ initialization

mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,

CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by

the CPU when the MSCAN is in initialization mode.

0 Running — The MSCAN operates normally

1 Initialization mode active — The MSCAN has entered initialization mode

76543210

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Reset:

00000000

Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0)

Table 10-3. CANBTR0 Register Field Descriptions

Field

Description

7:6

SJW[1:0]

Synchronization Jump Width — The synchronization jump width deﬁnes the maximum number of time quanta

(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the

CAN bus (see Table 10-4).

5:0

BRP[5:0]

Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing

(see Table 10-5).

Table 10-4. Synchronization Jump Width

SJW1

SJW0

Synchronization Jump Width

1 Tq clock cycle

2 Tq clock cycles

3 Tq clock cycles

4 Tq clock cycles

Table 10-2. CANCTL1 Register Field Descriptions (continued)

Field

Description

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