PC912XDP512F0MPVR datasheet(458/1348 Pages) FREESCALE

458 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

458

Freescale Semiconductor

10.4.2.1

Message Transmit Background

Modern application layer software is built upon two fundamental assumptions:

•

Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus

between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the

previous message and only release the CAN bus in case of lost arbitration.

•

The internal message queue within any CAN node is organized such that the highest priority

message is sent out ﬁrst, if more than one message is ready to be sent.

The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer

must be reloaded immediately after the previous message is sent. This loading process lasts a ﬁnite amount

of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted

stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts

with short latencies to the transmit interrupt.

A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending

and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a

message is ﬁnished while the CPU re-loads the second buffer. No buffer would then be ready for

transmission, and the CAN bus would be released.

At least three transmit buffers are required to meet the ﬁrst of the above requirements under all

circumstances. The MSCAN has three transmit buffers.

The second requirement calls for some sort of internal prioritization which the MSCAN implements with

the “local priority” concept described in Section 10.4.2.2, “Transmit Structures.”

10.4.2.2

Transmit Structures

The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple

messages to be set up in advance. The three buffers are arranged as shown in Figure 10-39.

All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see

Section 10.3.3, “Programmer’s Model of Message Storage”). An additional Section 10.3.3.4, “Transmit

Buffer Priority Register (TBPR) contains an 8-bit local priority ﬁeld (PRIO) (see Section 10.3.3.4,

“Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a

message, if required (see Section 10.3.3.5, “Time Stamp Register (TSRH–TSRL)”).

To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set

transmitter buffer empty (TXEx) ﬂag (see Section 10.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the

CANTBSEL register (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see

Section 10.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the

CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler

software simpler because only one address area is applicable for the transmit process, and the required

address space is minimized.

The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers.

Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag.

PC912XDP512F0MPVR 데이터시트(PDF) 458 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 458 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL