PC912XDP512F0MPVR datasheet(582/1348 Pages) FREESCALE

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Chapter 15 Background Debug Module (S12XBDMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

15.4.5

BDM Command Structure

Hardware and ﬁrmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a

16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte

or word implication in the command name.

8-bit reads return 16-bits of data, of which, only one byte will contain valid

data. If reading an even address, the valid data will appear in the MSB. If

reading an odd address, the valid data will appear in the LSB.

16-bit misaligned reads and writes are generally not allowed. If attempted

by BDM hardware command, the BDM will ignore the least signiﬁcant bit

of the address and will assume an even address from the remaining bits.

The following cycle count information is only valid when the external wait

function is not used (see wait bit of EBI sub-block). During an external wait

the BDM can not steal a cycle. Hence be careful with the external wait

function if the BDM serial interface is much faster than the bus, because of

the BDM soft-reset after time-out (see Section 15.4.11, “Serial

Communication Time Out”).

For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending

the address before attempting to obtain the read data. This is to be certain that valid data is available in the

BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait

150 bus clock cycles after sending the data to be written before attempting to send a new command. This

is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle

delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a

free cycle before stealing a cycle.

For ﬁrmware read commands, the external host should wait at least 48 bus clock cycles after sending the

command opcode and before attempting to obtain the read data. This includes the potential of extra cycles

when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port

replacement unit) in emulation mode. The 48 cycle wait allows enough time for the requested data to be

made available in the BDM shift register, ready to be shifted out.

NOTE

This timing has increased from previous BDM modules due to the new

capability in which the BDM serial interface can potentially run faster than

the bus. On previous BDM modules this extra time could be hidden within

the serial time.

For ﬁrmware write commands, the external host must wait 36 bus clock cycles after sending the data to be

written before attempting to send a new command. This is to avoid disturbing the BDM shift register

before the write has been completed.

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