PC912XDP512F0MPVR datasheet(623/1348 Pages) FREESCALE

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Chapter 17 Memory Mapping Control (S12XMMCV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

623

17.3.2.5

MMC Control Register (MMCCTL1)

Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other

modes the data are read from this register.

Write: Refer to each bit description. In emulation modes write operations will also be directed to the

external bus.

CAUTION

XGATE write access to this register during an CPU access which makes use

of this register could lead to unexpected results.

EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for

XGATE). Both local and global memory maps are affected.

Address: 0x0013 PRR

76543210

00000

EROMON

ROMHM

ROMON

Reset

00000

EROMCTL

ROMCTL

= Unimplemented or Reserved

Figure 17-10. MMC Control Register (MMCCTL1)

Table 17-9. MMCCTL1 Field Descriptions

Field

Description

EROMON

Enables emulated Flash or ROM memory in the memory map

Write: Never

0 Disables the emulated Flash or ROM in the memory map.

1 Enables the emulated Flash or ROM in the memory map.

ROMHM

FLASH or ROM only in higher Half of Memory Map

Write: Once in normal and emulation modes and anytime in special modes

0 The ﬁxed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to

$4000–$7FFF will be mapped to $7F_4000-$7F_7FFF in the global memory space.

1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the

Flash or ROM can still be accessed through the program page window. Accesses to $4000–$7FFF will be

mapped to $14_4000-$14_7FFF in the global memory space (external access).

ROMON

Enable FLASH or ROM in the memory map

Write: Once in normal and emulation modes and anytime in special modes

0 Disables the Flash or ROM from the memory map.

1 Enables the Flash or ROM in the memory map.

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