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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 629 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 629 Page - Freescale Semiconductor, Inc |
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629 / 1348 page  Chapter 17 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 629 17.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when RWPE = 0 17.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL) Read: Anytime Write: Anytime when RWPE = 0 Address: 0x011D 76543210 R1 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 W Reset 11111111 = Unimplemented or Reserved Figure 17-18. RAM XGATE Upper Boundary Register (RAMXGU) Table 17-15. RAMXGU Field Descriptions Field Description 6–0 XGU[6:0] XGATE Region Upper Boundary Bits 6-0 — These bits define the upper boundary of the RAM region allocated to the XGATE module in multiples of 256 bytes. The 256 byte block selected by this register is included in the region. See Figure 1-25 for details. Address: 0x011E 76543210 R1 SHL6 SHL5 SHL4 SHL3 SHL2 SHL1 SHL0 W Reset 11111111 = Unimplemented or Reserved Figure 17-19. RAM Shared Region Lower Boundary Register (RAMSHL) Table 17-16. RAMSHL Field Descriptions Field Description 6–0 SHL[6:0] RAM Shared Region Lower Boundary Bits 6–0 — These bits define the lower boundary of the shared memory region in multiples of 256 bytes. The block selected by this register is included in the region. See Figure 1-25 for details. |
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