PC912XDP512F0MPVR datasheet(652/1348 Pages) FREESCALE

652 / 1348 page

Chapter 18 Memory Mapping Control (S12XMMCV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

652

Freescale Semiconductor

18.1.1

Terminology

18.1.2

Features

The main features of this block are:

•

Paging capability to support a global 8 Mbytes memory address space

•

Bus arbitration between the masters CPU, BDM and XGATE

Table 18-1. Acronyms and Abbreviations

Logic level “1”

Voltage that corresponds to Boolean true state

Logic level “0”

Voltage that corresponds to Boolean false state

Represents hexadecimal number

Represents logic level ’don’t care’

byte

8-bit data

word

16-bit data

local address

based on the 64 KBytes Memory Space (16-bit address)

global address

based on the 8 MBytes Memory Space (23-bit address)

Aligned address

Address on even boundary

Mis-aligned address

Address on odd boundary

Bus Clock

System Clock. Refer to CRG Block Guide.

expanded modes

Normal Expanded Mode

Emulation Single-Chip Mode

Emulation Expanded Mode

Special Test Mode

single-chip modes

Normal Single-Chip Mode

Special Single-Chip Mode

emulation modes

Emulation Single-Chip Mode

Emulation Expanded Mode

normal modes

Normal Single-Chip Mode

Normal Expanded Mode

special modes

Special Single-Chip Mode

Special Test Mode

Normal Single-Chip Mode

Special Single-Chip Mode

Normal Expanded Mode

Emulation Single-Chip Mode

Emulation Expanded Mode

Special Test Mode

Unimplemented areas

Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented

External Space

Area which is accessible in the global address range 14_0000 to 3F_FFFF

external resource

Resources (Emulator, Application) connected to the MCU via the external bus on

expanded modes (Unimplemented areas and External Space)

PRR

Port Replacement Registers

PRU

Port Replacement Unit located on the emulator side

MCU

MicroController Unit

NVM

Non-volatile Memory; Flash EEPROM or ROM

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