PC912XDP512F0MPVR datasheet(672/1348 Pages) FREESCALE

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Chapter 18 Memory Mapping Control (S12XMMCV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

672

Freescale Semiconductor

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Normal expanded mode

The external bus interface is conﬁgured as an up to 23-bit address bus, 8 or 16-bit data bus with

dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and

peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal

bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by

the external logic.

•

Emulation expanded mode

Tool vendors use this mode for emulation systems in which the user’s target application is normal

expanded mode.

•

Special test mode

This mode is an expanded mode for factory test.

18.4.2

Memory Map Scheme

18.4.2.1

CPU and BDM Memory Map Scheme

The BDM ﬁrmware lookup tables and BDM register memory locations share addresses with other

modules; however they are not visible in the memory map during user’s code execution. The BDM

memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish

between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block

Guide for further details).

When the MCU enters active BDM mode, the BDM ﬁrmware lookup tables and the BDM registers

become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x7F_FF00 -

0x7F_FFFF) and the CPU begins execution of ﬁrmware commands or the BDM begins execution of

hardware commands. The resources which share memory space with the BDM module will not be visible

in the memory map during active BDM mode.

Please note that after the MCU enters active BDM mode the BDM ﬁrmware lookup tables and the BDM

registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value

of 0xFF.

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