PC912XDP512F0MPVR datasheet(683/1348 Pages) FREESCALE

683 / 1348 page

Chapter 18 Memory Mapping Control (S12XMMCV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

683

18.4.4.1

Master Bus Prioritization regarding Access Conﬂicts on Target Buses

The arbitration scheme allows only one master to be connected to a target at any given time. The following

rules apply when prioritizing accesses from different masters to the same target bus:

•

CPU always has priority over BDM and XGATE.

•

XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU

for its duration.

•

XGATE has priority over BDM.

•

BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the

later case the suspect master will be stalled after ﬁnishing the current operation and the BDM will

gain access to the bus.

•

In emulation modes all internal accesses are visible on the external bus as well and the external bus

is used during access to the PRU registers.

18.4.5

Interrupts

18.4.5.1

Outgoing Interrupt Requests

The following interrupt requests can be triggered by the MMC module:

CPU access violation: The CPU access violation signals to the CPU detection of an error condition in the

CPU application code which is resulted in write access to the protected XGATE RAM area (see

Section 18.4.3.2, “Illegal CPU Accesses).

18.5

Initialization/Application Information

18.5.1

CALL and RTC Instructions

CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the

program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is

called can be located anywhere in the local address space or in any Flash or ROM page visible through the

program page window. The CALL instruction calculates and stacks a return address, stacks the current

PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value

controls which of the 256 possible pages is visible through the 16 Kbyte program page window in the

64 Kbyte local CPU memory map. Execution then begins at the address of the called subroutine.

During the execution of the CALL instruction, the CPU performs the following steps:

1. Writes the current PPAGE value into an internal temporary register and writes the new

instruction-supplied PPAGE value into the PPAGE register

2. Calculates the address of the next instruction after the CALL instruction (the return address) and

pushes this 16-bit value onto the stack

3. Pushes the temporarily stored PPAGE value onto the stack

4. Calculates the effective address of the subroutine, reﬁlls the queue and begins execution at the new

address

PC912XDP512F0MPVR 데이터시트(PDF) 683 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 683 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL