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PC912XDP512F0MPVR 데이터시트(PDF) 728 Page - Freescale Semiconductor, Inc

부품명 PC912XDP512F0MPVR
상세설명  HCS12X Microcontrollers
PDF  1348 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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Chapter 19 S12X Debug (S12XDBGV2) Module
MC9S12XDP512 Data Sheet, Rev. 2.21
730
Freescale Semiconductor
19.4.7.2
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final
state. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the
execution stage of the instruction queue. If an end aligned trigger is selected or no tracing is enabled,
breakpoints can be generated immediately, depending on the state of the DBGBRK[n] bits.
If a begin or mid aligned tracing session is selected by the TSOURCE bits, breakpoints are requested when
the tracing session has completed, thus the breakpoint is requested only on completion of the subsequent
trace (see Table 19-44). If the BRK bit is set on the triggering channel, then the breakpoint is generated
immediately independent of tracing trigger alignment.
19.4.7.3
Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the final state is entered. Tracing trigger alignment is defined by the TALIGN
bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing
session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace. If no tracing session is selected, breakpoints are requested
immediately. TRIG breakpoints are possible even if the DBG module is disarmed. TRIG bit breakpoints
are enabled by setting DBGBRK[n].
19.4.7.4
Breakpoints via TAGHI Or TAGLO Pin Taghits
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is
always end aligned, independent of internal channel trigger alignment configuration. External tag
breakpoints are always mapped to the CPU, are only possible in emulation modes and can be enabled by
setting DBGBRK[1].
Table 19-44. Setup for Both XGATE and CPU Breakpoints
BRK
TALIGN
DBGBRK[n]
Type of Debug Session
0
00
0
Fill trace buffer until trigger
(no breakpoints — keep running)
0
00
1
Fill trace buffer until trigger, then a breakpoint request occurs
0
01
0
Start trace buffer at trigger
(no breakpoints — keep running)
0
01
1
Start trace buffer at trigger
A breakpoint request occurs when trace buffer is full
0
10
0
Start trace buffer at trigger
End tracing 32 line entries after trigger
(no breakpoints — keep running)
0
10
1
Start trace buffer at trigger
End tracing 32 line entries after trigger
Request breakpoint after the 32 further trace buffer entries
1
00,01,10
0
Terminate tracing immediately on trigger without breakpoint
1
00,01,10
1
Terminate tracing and generate breakpoint immediately on trigger
x
11
x
Reserved



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