PC912XDP512F0MPVR datasheet(810/1348 Pages) FREESCALE

810 / 1348 page

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

812

Freescale Semiconductor

PK[7]

ROMCTL1

ROMON bit control input during RESET

Mode

dependent3

EWAIT

External Wait signal

Conﬁgurable for reduced input threshold

GPIO

I/O

General-purpose I/O

PK[6:4]

ADDR[22:20]

mux

ACC[2:0]2

Extended external bus address output

(multiplexed with access master output)

GPIO

I/O

General-purpose I/O

PK[3:0]

ADDR[19:16]

mux

IQSTAT[3:0]2

Extended external bus address output

(multiplexed with instruction pipe status bits)

GPIO

I/O

General-purpose I/O

PT[7:0]

IOC[7:0]

I/O

Enhanced Capture Timer Channels 7–0 input/output

GPIO

I/O

General-purpose I/O

PS7

SS0

I/O

Serial Peripheral Interface 0 slave select output in master

mode, input in slave mode or master mode.

GPIO

I/O

General-purpose I/O

PS6

SCK0

I/O

Serial Peripheral Interface 0 serial clock pin

GPIO

I/O

General-purpose I/O

PS5

MOSI0

I/O

Serial Peripheral Interface 0 master out/slave in pin

GPIO

I/O

General-purpose I/O

PS4

MISO0

I/O

Serial Peripheral Interface 0 master in/slave out pin

GPIO

I/O

General-purpose I/O

PS3

TXD1

Serial Communication Interface 1 transmit pin

GPIO

I/O

General-purpose I/O

PS2

RXD1

Serial Communication Interface 1 receive pin

GPIO

I/O

General-purpose I/O

PS1

TXD0

Serial Communication Interface 0 transmit pin

GPIO

I/O

General-purpose I/O

PS0

RXD0

Serial Communication Interface 0 receive pin

GPIO

I/O

General-purpose I/O

Table 22-1. Pin Functions and Priorities (Sheet 3 of 7)

Port

Pin Name

Pin Function

and Priority

I/O

Description

Pin Function

after Reset

PC912XDP512F0MPVR 데이터시트(PDF) 810 Page - Freescale Semiconductor, Inc

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