PC912XDP512F0MPVR datasheet(882/1348 Pages) FREESCALE

882 / 1348 page

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

884

Freescale Semiconductor

22.4.2.3

Port C and D

Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin

packages, also with the external bus interface. In this case port C and port D are associated with the

external data bus inputs/outputs DATA15–DATA8 and DATA7–DATA0, respectively.

These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI

section).

NOTE

Port C and D are neither available in 112-pin nor in 80-pin packages.

22.4.2.4

Port E

Port E is associated with the external bus control outputs R/W, LSTRB, LDS and RE, the free-running

clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and

interrupt inputs IRQ and XIRQ.

Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.

Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output

running at the core clock rate. The clock output is always enabled in emulation modes.

Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output

running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled

in emulation modes.

Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ

interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (Section 22.3.2.14, “IRQ

Control Register (IRQCR)”) and clearing the I-bit in the CPU’s condition code register. It is inhibited at

reset so this pin is initially configured as a simple input with a pull-up.

Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt

input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at

reset so this pin is initially configured as a high-impedance input with a pull-up.

Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to

S12X_EBI section).

22.4.2.5

Port K

Port K pins PK[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the

external bus interface. In this case port K pins PK[6:0] are associated with the external address bus outputs

ADDR22–ADDR16 and PK7 is associated to the EWAIT input.

Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).

NOTE

Port K is not available in 80-pin packages. PK[6] is not available in 112-pin

packages.

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