PC912XDP512F0MPVR datasheet(908/1348 Pages) FREESCALE

908 / 1348 page

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

910

Freescale Semiconductor

Memory Map and Register Deﬁnition

This section provides a detailed description of all PIMregisters.

23.0.4

Module Memory Map

Table 23-2 shows the register map of the port integration module.

PJ7

TXCAN4

MSCAN4 transmit pin

GPIO

SCL0

Inter Integrated Circuit 0 serial clock line

TXCAN0

MSCAN0 transmit pin

GPIO/KWJ7

I/O

General-purpose I/O with interrupt

PJ6

RXCAN4

MSCAN4 receive pin

SDA0

I/O

Inter Integrated Circuit 0 serial data line

RXCAN0

MSCAN0 receive pin

GPIO/KWJ6

I/O

General-purpose I/O with interrupt

PJ5

CS2

Chip select 2

GPIO/KWJ7

I/O

General-purpose I/O with interrupt

PJ4

CS0

Chip select 0

GPIO/KWJ6

I/O

General-purpose I/O with interrupt

PJ2

CS1

Chip select 1

GPIO/KWJ2

I/O

General-purpose I/O with interrupt

PJ1

TXD2

Serial Communication Interface 2 transmit pin

GPIO/KWJ1

I/O

General-purpose I/O with interrupt

PJ0

RXD2

Serial Communication Interface 2 receive pin

CS3

Chip select 3

GPIO/KWJ0

I/O

General-purpose I/O with interrupt

AD0

PAD[07:00]

GPIO

I/O

General-purpose I/O

GPIO

AN[7:0]

ATD0 analog inputs

AD1

PAD[23:08]

GPIO

I/O

General-purpose I/O

GPIO

AN[15:0]

ATD1 analog inputs

1. Function active when RESET asserted.

2. Only available in emulation modes or in Special Test Mode with IVIS on.

3. Refer also to Table 23-70 and S12X_EBI section.

Table 23-1. Pin Functions and Priorities (Sheet 7 of 7)

Port

Pin Name

Pin Function

and Priority

I/O

Description

Pin Function

after Reset

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