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PC912XDP512F0MPVR 데이터시트(PDF) 976 Page - Freescale Semiconductor, Inc

부품명 PC912XDP512F0MPVR
상세설명  HCS12X Microcontrollers
PDF  1348 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 976 Page - Freescale Semiconductor, Inc

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
978
Freescale Semiconductor
External Signal Description
This section lists and describes the signals that do connect off-chip.
24.0.3
Signal Properties
Table 24-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section ,
“Functional Description” for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 24-1. Pin Functions and Priorities (Sheet 1 of 5)
Port
Pin Name
Pin Function
and Priority
I/O
Description
Pin Function
after Reset
—
BKGD
MODC1
I
MODC input during RESET
BKGD
BKGD
I/O
S12X_BDM communication pin
A
PA[7:0]
GPIO
I/O
General-purpose I/O
GPIO
B
PB[7:0]
GPIO
I/O
General-purpose I/O
GPIO
E
PE[7]
XCLKS1
I
External clock selection input during RESET
ECLKX2
I
Free-running clock output at Core Clock rate (ECLK x 2)
GPIO
I/O
General-purpose I/O
PE[6:5]
GPIO
I/O
General-purpose I/O
PE[4]
ECLK
O
Free-running clock output at the Bus Clock rate or
programmable divided in normal modes
GPIO
I/O
General-purpose I/O
PE[3:2]
GPIO
I/O
General-purpose I/O
PE[1]
IRQ
I
Maskable level- or falling edge-sensitive interrupt input
GPIO
I/O
General-purpose I/O
PE[0]
XIRQ
I
Non-maskable level-sensitive interrupt input
GPIO
I/O
General-purpose I/O
K
PK[7]
GPIO
I/O
General-purpose I/O
GPIO
PK[5:0]
GPIO
I/O
General-purpose I/O
T
PT[7:0]
IOC[7:0]
I/O
Enhanced Capture Timer Channels 7–0 input/output
GPIO
GPIO
I/O
General-purpose I/O



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