PC912XDP512F0MPVR datasheet(991/1348 Pages) FREESCALE

991 / 1348 page

24.0.5.2

Port B Data Register (PORTB)

Read: Anytime.

Write: Anytime.

24.0.5.3

Port A Data Direction Register (DDRA)

Read: Anytime.

Write: Anytime.

Table 24-4. PORTA Field Descriptions

Field

Description

7–0

PA[7:0]

Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins

are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.

76543210

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Reset

00000000

Figure 24-4. Port B Data Register (PORTB)

Table 24-5. PORTB Field Descriptions

Field

Description

7–0

PB[7:0]

Port B — Port B pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O

pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state

is read.

76543210

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Reset

00000000

Figure 24-5. Port A Data Direction Register (DDRA)

Table 24-6. DDRA Field Descriptions

Field

Description

7–0

DDRA[7:0]

Data Direction Port A — This register controls the data direction for port A. DDRA determines whether each pin

is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes

the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTA after changing the DDRA register.

PC912XDP512F0MPVR 데이터시트(PDF) 991 Page - Freescale Semiconductor, Inc

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