PC912XDP512F0MPVR datasheet(1031/1348 Pages) FREESCALE

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24.0.7.9

Port H

This port is associated with the SPI1, . Port H pins PH[7:0] can be used for either general purpose

I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1. Refer to

Section 24.0.5.33, “Module Routing Register (MODRR)”.

Port H offers 8 I/O pins with edge triggered interrupt capability (Section 24.0.8, “Pin Interrupts”).

NOTE

Port H is not available in 80-pin packages.

24.0.7.10 Port J

This port is associated with CAN4, CAN0, IIC0. Port J pins PJ[7:4] and PJ[2:0] can be used for

either general purpose I/O, or with the CAN, IIC, or SCI subsystems. If IIC takes precedence the

associated pins become IIC open-drain output pins. The CAN4 pins can be re-routed. Refer to

Section 24.0.5.33, “Module Routing Register (MODRR)”.

Port J pins can be used with the routed CAN0 modules. Refer to Section 24.0.5.33, “Module

Routing Register (MODRR)”.

Port J offers 7 I/O pins with edge triggered interrupt capability (Section 24.0.8, “Pin Interrupts”).

NOTE

PJ[5,4,2,1,0] are not available in 80-pin packages.

24.0.7.11 Port AD1

This port is associated with the ATD1. Port AD1 pins PAD15–PAD0 can be used for either general

purpose I/O, or with the ATD1 subsystem.

NOTE

PAD[15:8] are not available in 80-pin packages.

24.0.8

Pin Interrupts

Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to

rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share

the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.

An interrupt is generated when a bit in the port interrupt flag register and its corresponding port

interrupt enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when

it is in STOP or WAIT mode.

A digital filter on each pin prevents pulses (Figure 24-70) shorter than a specified time from

generating an interrupt. The minimum time varies over process conditions, temperature and

voltage (Figure 24-69 and Table 24-62).

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