PC912XDP512F0MPVR datasheet(107/1348 Pages) FREESCALE

107 / 1348 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

107

Table 2-12. Outcome of Clock Loss in Wait Mode

CME

SCME

SCMIE

CRG Actions

Clock failure -->

No action, clock loss not detected.

Clock failure -->

CRG performs Clock Monitor Reset immediately

Clock failure -->

Scenario 1: OSCCLK recovers prior to exiting wait mode.

– MCU remains in wait mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag.

Some time later OSCCLK recovers.

– CM no longer indicates a failure,

– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,

– SCM deactivated,

– PLL disabled depending on PLLWAI,

– VREG remains enabled (never gets disabled in wait mode).

– MCU remains in wait mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit wait mode using OSCCLK as system clock (SYSCLK),

– Continue normal operation.

or an External Reset is applied.

– Exit wait mode using OSCCLK as system clock,

– Start reset sequence.

Scenario 2: OSCCLK does not recover prior to exiting wait mode.

– MCU remains in wait mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag,

– Keep performing clock quality checks (could continue inﬁnitely) while in wait mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit wait mode in SCM using PLL clock (fSCM) as system clock,

– Continue to perform additional clock quality checks until OSCCLK is o.k. again.

or an External RESET is applied.

– Exit wait mode in SCM using PLL clock (fSCM) as system clock,

– Start reset sequence,

– Continue to perform additional clock quality checks until OSCCLKis o.k.again.

Clock failure -->

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– SCMIF set.

SCMIF generates self clock mode wakeup interrupt.

– Exit wait mode in SCM using PLL clock (fSCM) as system clock,

– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.

PC912XDP512F0MPVR 데이터시트(PDF) 107 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 107 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL