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PC912XDP512F0MPVR 데이터시트(PDF) 1078 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 1078 Page - Freescale Semiconductor, Inc |
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1078 / 1348 page ![]() Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev. 2.21 1080 Freescale Semiconductor All bits read 0 and are not writable. 26.3.2.4 EEPROM Configuration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable. 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 26-6. RESERVED2 76543210 R CBEIE CCIE 000000 W Reset 00000000 = Unimplemented or Reserved Figure 26-7. EEPROM Configuration Register (ECNFG) Table 26-4. ECNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the EEPROM module. 0 Command Buffer Empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”) is set. 6 CCIE Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the EEPROM module. 0 Command Complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”) is set. |
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