PC912XDP512F0MPVR datasheet(1206/1348 Pages) FREESCALE

1206 / 1348 page

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)

MC9S12XDP512 Data Sheet, Rev. 2.21

1208

Freescale Semiconductor

All bits read 0 and are not writable.

29.3.2.14 RESERVED4

This register is reserved for factory testing and is not accessible.

All bits read 0 and are not writable.

29.4

Functional Description

29.4.1

Flash Command Operations

Write operations are used to execute program, erase, erase verify, erase abort, and data compress

algorithms described in this section. The program and erase algorithms are controlled by a state machine

whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command

FIFO) so that a second command along with the necessary data and address can be stored to the buffer

while the ﬁrst command is still in progress. This pipelined operation allows a time optimization when

programming more than one word on a speciﬁc row in the Flash block as the high voltage generation can

be kept active in between two programming commands. The pipelined operation also allows a

simpliﬁcation of command launching. Buffer empty as well as command completion are signalled by ﬂags

in the Flash status register with corresponding interrupts generated, if enabled.

The next sections describe:

1. How to write the FCLKDIV register

2. Command write sequences to program, erase, erase verify, erase abort, and data compress

operations on the Flash memory

3. Valid Flash commands

4. Effects resulting from illegal Flash command write sequences or aborting Flash operations

76543210

00000000

Reset

00000000

= Unimplemented or Reserved

Figure 29-20. RESERVED3

76543210

00000000

Reset

00000000

= Unimplemented or Reserved

Figure 29-21. RESERVED4

PC912XDP512F0MPVR 데이터시트(PDF) 1206 Page - Freescale Semiconductor, Inc