PC912XDP512F0MPVR datasheet(153/1348 Pages) FREESCALE

153 / 1348 page

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

153

4.4.1.2

Analog Input Multiplexer

The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold

machine.

4.4.1.3

Sample Buffer Ampliﬁer

The sample ampliﬁer is used to buffer the input analog signal so that the storage node can be quickly

charged to the sample potential.

4.4.1.4

Analog-to-Digital (A/D) Machine

The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8

or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the

stored analog sample potential with a series of digitally generated analog potentials. By following a binary

search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled

potential.

When not converting the A/D machine disables its own clocks. The analog electronics continue drawing

quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog

power consumption.

Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result

in a non-railed digital output codes.

4.4.2

Digital Sub-Block

This subsection explains some of the digital features in more detail. See register descriptions for all details.

4.4.2.1

External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to the external environment

events rather than relying on software to signal the ATD module when ATD conversions are to take place.

The external trigger signal (out of reset ATD channel 15, conﬁgurable in ATDCTL1) is programmable to

be edge or level sensitive with polarity control. Table 4-27 gives a brief description of the different

combinations of control bits and their effect on the external trigger function.

During a conversion, if additional active edges are detected the overrun error ﬂag ETORF is set.

Table 4-27. External Trigger Control Bits

ETRIGLE

ETRIGP

ETRIGE

SCAN

Description

Ignores external trigger. Performs one conversion sequence and stops.

Ignores external trigger. Performs continuous conversion sequences.

Falling edge triggered. Performs one conversion sequence per trigger.

Rising edge triggered. Performs one conversion sequence per trigger.

Trigger active low. Performs continuous conversions while trigger is active.

Trigger active high. Performs continuous conversions while trigger is active.

PC912XDP512F0MPVR 데이터시트(PDF) 153 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 153 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL