PC912XDP512F0MPVR datasheet(160/1348 Pages) FREESCALE

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

160

Freescale Semiconductor

5.1.2.2

MCU Operating Modes

•

Stop mode

Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power

standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,

there must be a minimum delay for the stop recovery time tSR before initiating a new ATD

conversion sequence.

•

Wait mode

Entering wait mode the ATD conversion either continues or aborts for low power depending on the

logical value of the AWAIT bit.

•

Freeze mode

In freeze mode the ATD will behave according to the logical values of the FRZ1 and FRZ0 bits.

This is useful for debugging and emulation.

5.1.3

Block Diagram

Figure 5-1 shows a block diagram of the ATD.

5.2

External Signal Description

This section lists all inputs to the ATD block.

5.2.1

ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin

This pin serves as the analog input channel x. It can also be conﬁgured as general purpose digital port pin

and/or external trigger for the ATD conversion.

5.2.2

ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion.

Refer to the device overview chapter for availability and connectivity of these inputs.

5.2.3

VRH and VRL — High and Low Reference Voltage Pins

VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion.

5.2.4

VDDA and VSSA — Power Supply Pins

These pins are the power supplies for the analog circuitry of the ATD block.

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