PC912XDP512F0MPVR datasheet(189/1348 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

189

6.3.1.1

XGATE Control Register (XGMCTL)

All module level switches and flags are located in the module control register Figure 6-3.

Read: Anytime

Write: Anytime

00000000

XGE

XGFRZ XGDBG XGSS XGFACT

SWEIF

XGIE

XGEM

FRZM

DBGM

SSM

FACTM

SWEIFM

XGIEM

Reset

0000000000000

= Unimplemented or Reserved

Figure 6-3. XGATE Control Register (XGMCTL)

Table 6-1. XGMCTL Field Descriptions (Sheet 1 of 3)

Field

Description

XGEM

XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is

written to the XGEM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGE in the same bus cycle

1 Enable write access to the XGE in the same bus cycle

XGFRZM

XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared

if a "1" is written to the XGFRZM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGFRZ in the same bus cycle

1 Enable write access to the XGFRZ in the same bus cycle

XGDBGM

XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared

if a "1" is written to the XGDBGM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGDBG in the same bus cycle

1 Enable write access to the XGDBG in the same bus cycle

XGSSM

XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a

"1" is written to the XGSSM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGSS in the same bus cycle

1 Enable write access to the XGSS in the same bus cycle

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