STM6502LEABDG6F datasheet(18/29 Pages) STMICROELECTRONICS

18 / 29 page

DC and AC parameters

STM6502, STM6503, STM6504, STM6505

18/29

Doc ID 16101 Rev 5

Smart Reset inputs

VIL

SR0, SR1, SRE input

voltage low

VSS

–0.3

0.3

VCC

VIH

SR0, SR1, SRE input

voltage high

0.7

VCC

5.5

ILI(SR)

Input leakage current, SR

and SRE inputs

Option without internal pull-up resistor

–1

µA

ILI(TSR)

Input leakage current, TSR

input

STM6503 and STM6504 only

–5

µA

RPUI

Internal pull-up resistor,

input (optional - refer to

Table 12)

tDEBOUNCE

SRE input falling edge

debounce time

STM6504 only

240

360

480

Smart Reset delay

tSRC

(5)

Capacitor-programmable

Smart Reset setup time,

STM6502 and STM6505.

Refer to Table 3.

TA = 25 °C

10 x

CSRC

(µF)

12.5 x

CSRC

(µF)

15 x

CSRC

(µF)

tSRC

(5)

TSR pin-programmable

Smart Reset setup time,

STM6503 and STM6504.

TSR = VSS

22.5

TSR = floating(6)

67.5

TSR = VCC

12.5

Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted).

Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.

For devices with VRST < 3.0 V.

Guaranteed by design.

Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505

only.

If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic

capacitor between the TSR and VSS pins.

Table 6.

DC and AC characteristics (continued)

Symbol

Parameter

Test conditions(1)

Min.

Typ.(2)

Max.

Unit

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