DAC5682Z datasheet(3/59 Pages) TI

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DAC5682Z

GND

CLKINC

D4P

D4N

D3P

D3N

D2P

D2N

DVDD

D1P

D1N

D0P

D0N

VFUSE

SDO

SDIO

SCLK

SDENB

D12N

D12P

D13N

D13P

D14N

D14P

DVDD

D15N

D15P

IOVDD

SYNCN

SYNCP

CLKIN

CLKVDD

DAC5682Z

www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009

DAC5682Z

RGC PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

51, 54, 55,

Analog supply voltage. (3.3V)

AVDD

59, 62

BIASJ

Full-scale output current bias. For 20mA full-scale output current, connect a 960

Ω resistor to GND.

Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL

CLKIN

enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides

clock for DAC up to 1GHz.

CLKINC

Complementary external clock input. (See the CLKIN description)

CLKVDD

Internal clock buffer supply voltage. (1.8 V)

LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100

Ω

7, 11, 13,

termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative

15, 17, 19,

to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In

21, 23, 27,

D[15..0]P

dual-channel mode, data for the A-channel is input while DCLKP is high.

29, 31, 33,

35, 37, 40,

D15P is most significant data bit (MSB) – pin 7

D0P is least significant data bit (LSB) – pin 42

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