SA3488 datasheet(9/20 Pages) SAMES

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SA3488

sames

Pin Description (Cont.)

Designation

Description

RESET

This pin is used to initialise the device. The initialisation

routine takes one time frame whatever the RESET pulse

width (one clock cycle minimum). All internal registers are

set 'high' and the control memory is set to all 'ones' i.e.

channel disconnection. The data bus is pulled to a high

impedance state as well as the PCM output channels.

DR is the data ready pin which is normally high. If DR goes

low the following information is available via this pin.

1. Invalid instruction code (The pin is held low until a valid

instruction is loaded).

2. An active output channel was found in a matrix of

devices with the same CS pins during the execution of

instruction 5. DR is low for two clock cycles.

3. Status register 2 was loaded with the total number of

messages in time slot 0 during the execution of

instruction

6. DR is active low for two clock cycles.

CLOCK

Input clock frequency is typically 4.096Mhz. This signal

will set the internal input/ output channel bit rate to 2.048

Mbits/sec. The bit rate is set by division of the master

clock frequency.

SYNC

The input synchronisation signal frequency is 8kHz and is

active low. Internally generated time bases that maintain

sequential addressing are synchonised via the SYNC

signal.

INP PCM7

The input PCM bus accepts a standard data rate of 2MBits/

sec.

INP PCM6

INP PCM5

INP PCM4

INP PCM3

INP PCM2

INP PCM1

INP PCM0

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