SA9101 datasheet(31/40 Pages) SAMES

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SA9101

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ADR 6

Additional Receive Status

Bit

Description

Name

SR6B6

Error On Primary Rate Line Receiver

This bit is set while both dual rail inputs are active.

SR6B[0-5,7]

0-5,7

Not used, set to "1".

ADR 7

Timeslot 16 Rx Stack

Bit

Description

Name

SR7B[0-7]

0-7

Receive Signalling Data

This stack contains two bytes of sequentially received signalling

data (timeslot 16).

ADR 8

i-bits

Bit

Description

Name

SR8B0

Si(II)

Bit will be set to "0" if a CRC

check gives an error or synchro-

nisation is lost. It will be set to

These bits are

"1", if no error is detected in

updated at the

sub-multiframe part II.

beginning of every

SR8B1

Si(I)

received CRC

Bit will be set to "0", if a CRC

multiframe. If the

check gives an error or synchro-

device is in double-

nisation is lost. It will be set to

frame format, these

"1", if no error is detected in

bits are fixed to "1".

sub-multiframe part I.

SR8B[2-7]

2-7

Not used

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