PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

14

99-06-15

♦ Phase Detector Polarity

Depending on VCO characteristics, R16 bit should be set

as follows :

VCO characteristics are positive like (1) : R16 HIGH

VCO characteristics are negative like (2) : R16 LOW

♦ foLD (Pin10) Output Truth Table

- When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses

LOW.

- Counter Reset mode resets R & N counters.

- The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance

(

≤110

Ω).

RF R19

(RF LD)

IF R19

(IF LD)

RF R20

(RF fo)

IF R20

(IF fo)

foLD Output State

0

0

0

0

Disabled (default LOW)

0

1

0

0

IF Lock Detect

1

0

0

0

RF Lock Detect

1

1

0

0

RF and IF Lock Detect

0

0

0

1

IF Reference Divider Output

0

0

1

0

RF Reference Divider Output

0

1

0

1

IF Programmable Divider Output

0

1

1

0

RF Programmable Divider Output

0

0

1

1

High Speed Lock mode

0

1

1

1

IF Counter Reset

1

0

1

1

RF Counter Reset

1

1

1

1

RF and IF Counter Reset

(1)

(2)

VCO Input Voltage

VCO Characteristics