S5T8808A

PLL FREQUENCY SHNTHESIZER FOR PAGE

6

FUNCTIONAL DESCTRIPTION

Figure 1. Rx. Register Programming Timing

•

Programmable N-counter consists of 2-bits Swallow Counter, 4/5 Dual modulars Prescaler and 14-bits Main

Counter

•

The Divide Ratio is;

N = (P + 1)

× S + P (M − S) = PM + S;

— P = Dual Modulars Prescaler (4)

— S = 2-bits Swallow Counter value (0 ~ 3)

— M = 14-bits (7 ~ 16383)

— N = Programmable N-Counter value (N > S; 28 ~ 65535)

Table 1. N-Counter Register Program Scheme (17 bits)

Bit

Bit 16 (ND 15) ~ Bit 1 (ND 0)

Bit 0 (LSB)

Name

RxD

PMC

Description

Rx. Program Data (ND 15 ~ ND 0)

Program Mode Control

Function

16 Bit Programmable Rx. N-Counter Data

0: Rx. N-Counter

1: Ref. R-Counter

PMC

DATA

Rx.16Bit N_Counter Data ( ND15 ~ ND0 )

EN1

or

EN2

CLK

positive

edge

triggered

LSB

MSB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

PMC = 0

→ 16-bit N_Counter