AT90PWM2 datasheet(140/361 Pages) ATMEL

140 / 361 page

140

4317J–AVR–08/10

AT90PWM2/3/2B/3B

fractional divider number. The resulting output frequency is the average of the frequencies in the

frame. The fractional divider (d) is given by OCRnRB[15:12].

The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0)

and PSCOUTn1 On Time + DeadTime (OT1+DT1) values. These values are 12 bits numbers.

The frequency adjustment can only be done in steps like the dedicated counters. The step width

is defined as the frequency difference between two neighboring PSC frequencies:

with k is the number of CLKPSC period in a PSC cycle and is given by the following formula:

with fOP is the output operating frequency.

Exemple, in normal mode, with maximum operating frequency 160 kHz and fPLL = 64 Mhz, k

equals 400. The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.

In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu-

tive cycles.

fb1 and fb2 are two neightboring base frequencies.

Then the frequency resolution is divided by 16. In the example above, the resolution equals 25

Hz.

Δff1 f2

–

fPLL

----------

fPLL

k 1

------------

–

fPSC

kk 1

()

--------------------

fPSC

fOP

----------

fAVERAGE

–

---------------

fb1

------

fb2

fAVERAGE

–

---------------

fPLL

----------

------

fPLL

n 1

------------

AT90PWM2 데이터시트(PDF) 140 Page - ATMEL Corporation

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