AT90PWM2 datasheet(205/361 Pages) ATMEL

205 / 361 page

205

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Receiver will generate a parity value for the incoming data and compare it to the UPM setting. If

a mismatch is detected, the UPE Flag in UCSRA will be set.

This setting is available in EUSART mode only when data bits are level encoded (in Manchester

the parity checker and generator are not available).

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

In EUSART mode, the USBS bit has the same behavior and the EUSB bit of the EUSART allows

to configure the number of stop bit for the receiver in this mode.

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-

acter SiZe) in a frame the Receiver and Transmitter use.

When the EUSART mode is set, these bits have no effect.

• Bit 0 – UCPOL: Clock Polarity

Table 18-5.

UPM Bits Settings

UPM1

UPM0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 18-6.

USBS Bit Settings

USBS

Stop Bit(s)

01-bit

12-bit

Table 18-7.

UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

5-bit

6-bit

7-bit

8-bit

100

Reserved

101

Reserved

110

Reserved

9-bit

AT90PWM2 데이터시트(PDF) 205 Page - ATMEL Corporation

AT90PWM2 데이터시트(HTML) 205 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL