AT90PWM2 datasheet(206/361 Pages) ATMEL

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206

4317J–AVR–08/10

AT90PWM2/3/2B/3B

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOL bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

18.10.5

USART Baud Rate Registers – UBRRL and UBRRH

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four

most significant bits, and the UBRRL contains the eight least significant bits of the USART baud

rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is

changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.

18.11 Examples of Baud Rate Setting

For standard crystal, resonator and external oscillator frequencies, the most commonly used

baud rates for asynchronous operation can be generated by using the UBRR settings in Table

18-9 up to Table 18-12. UBRR values which yield an actual baud rate differing less than 0.5%

from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the

Receiver will have less noise resistance when the error ratings are high, especially for large

serial frames (see “Asynchronous Operational Range” on page 199). The error values are calcu-

lated using the following equation:

Table 18-8.

UCPOL Bit Settings

UCPOL

Transmitted Data Changed

(Output of TxDn Pin)

Received Data Sampled

(Input on RxD Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Bit

13121110

––––

UBRR[11:8]

UBRRH

UBRR[7:0]

UBRRL

76543210

Read/Write

RRRR

R/W

Initial Value

00000000

Error[%]

BaudRate

Closest Match

BaudRate

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