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ADF7242BCPZ 데이터시트(PDF) 13 Page - Analog Devices

부품명 ADF7242BCPZ
상세설명  Low Power IEEE 802.15.4/Proprietary GFSK/FSK Zero-IF 2.4 GHz Transceiver IC
PDF  108 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADF7242BCPZ 데이터시트(HTML) 13 Page - Analog Devices

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ADF7242
Rev. 0 | Page 13 of 108
TIMING AND DIGITAL SPECIFICATIONS
Table 7. Logic Levels
Parameter
Min
Typ
Max
Unit
Test Conditions
LOGIC INPUTS
Input High Voltage, VINH
0.7 × VDD_BAT
V
Input Low Voltage, VINL
0.2 × VDD
V
Input Current, IINH/IINL
±1
μA
Input Capacitance, CIN
10
pF
LOGIC OUTPUTS
Output High Voltage, VOH
VDD_BAT − 0.4
V
IOH = 500 μA
Output Low Voltage, VOL
0.4
V
IOL = 500 μA
Output Rise/Fall
5
ns
Output Load
7
pF
Table 8. GPIOs
Parameter
Min
Typ
Max
Unit
Test Conditions
GPIO OUTPUTS
Output Drive Level
5
mA
All GPIOs in logic high state
Output Drive Level
5
mA
All GPIOs in logic low state
Table 9. SPI Interface Timing
Parameter
Min
Typ
Max
Unit
Description
t1
15
ns
CS falling edge to MISO setup time (TRX active)
t2
40
ns
CS to SCLK setup time
t3
40
ns
SCLK high time
t4
40
ns
SCLK low time
t5
80
ns
SCLK period
t6
10
ns
SCLK falling edge to MISO delay
t7
5
ns
MOSI to SCLK rising edge setup time
t8
5
ns
MOSI to SCLK rising edge hold time
t9
40
ns
SCLK to CS hold time
t10
10
ns
CS high to SCLK wait time
t11
270
ns
CS high time
t12
300
400
μs
CS low to MISO high wake-up time, 26 MHz crystal with 10 pF load capacitance, TA = 25°C
t13
20
ns
SCLK rise time
t14
20
ns
SCLK fall time
t15, t16
2
ms
CS high time on wake-up after RC_RESET or RC_SLEEP command (see Figure 5 and
Figure 70) 26 MHz crystal with 10 pF load



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