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ADIS16305/PCBZ 데이터시트(PDF) 5 Page - Analog Devices

부품명 ADIS16305/PCBZ
상세설명  Precision Four Degrees of Freedom Sensor
PDF  20 Pages
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ADIS16305/PCBZ 데이터시트(HTML) 5 Page - Analog Devices

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ADIS16305
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Normal Mode
(SMPL_PRD ≤ 0x09)
Low Power Mode
(SMPL_PRD ≥ 0x0A)
Burst Read
Parameter
Description
Min1
Typ
Max
Min1
Typ
Max
Min1
Typ
Max
Unit
fSCLK
Serial clock
0.01
2.0
0.01
0.3
0.01
1.0
MHz
tSTALL
Stall period between data
9
75
1/fSCLK
μs
tREADRATE
Read rate
40
100
μs
t
CS
Chip select to clock edge
48.8
48.8
48.8
ns
tDAV
DOUT valid after SCLK edge
100
100
100
ns
tDSU
DIN setup time before SCLK rising edge
24.4
24.4
24.4
ns
tDHD
DIN hold time after SCLK rising edge
48.8
48.8
48.8
ns
tSCLKR, tSCLKF
SCLK rise/fall times (not shown in figures)
5
12.5
5
12.5
5
12.5
ns
tDR, tDF
DOUT rise/fall times (not shown in figures)
5
12.5
5
12.5
5
12.5
ns
tSFS
CS high after SCLK edge
5
5
5
ns
t1
Input sync positive pulse width
5
5
μs
tx
Input sync low time
100
100
μs
t2
Input sync to data-ready output
600
600
μs
t3
Input sync period
833
833
μs
1 Guaranteed by design and characterization, but not tested in production.
Timing Diagrams
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
R/W
A5
A6
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tDHD
tDSU
Figure 2. SPI Timing and Sequence
CS
SCLK
tREADRATE
tSTALL
Figure 3. Stall Time and Data Rate
t3
tX
t2
t1
SYNC
CLOCK (DIO4)
DATA
READY
Figure 4. Input Clock Timing Diagram



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